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?2006 integrated device technology, inc. january 2006 dsc 2746/12 1 high speed 2k x 16 dual-port sram idt7133sa/la idt7143sa/la features high-speed access ? military: 25/35/45/55/70/90ns (max.) ? industrial: 25/35/55ns (max.) ? commercial: 20/25/35/45/55/70/90ns (max.) low-power operation ? idt7133/43sa active: 1150mw (typ.) standby: 5mw (typ.) ? idt7133/43la active: 1050mw (typ.) standby: 1mw (typ.) versatile control for write: separate write control for lower and upper byte of each port master idt7133 easily expands data bus width to 32 bits or more using slave idt7143 on-chip port arbitration logic (idt7133 only) functional block diagram note: 1. idt7133 (master): busy is open drain output and requires pull-up resistor. idt7143 (slave): busy is input. busy output flag on idt7133; busy input on idt7143 fully asynchronous operation from either port battery backup operation?2v data retention ttl-compatible; single 5v (10%) power supply available in 68-pin ceramic pga, flatpack, plcc and 100- pin tqfp military product compliant to mil-prf-38535 qml industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information description the idt7133/7143 are high-speed 2k x 16 dual-port static rams. the idt7133 is designed to be used as a stand-alone 16-bit dual-port i/o control memory array arbitration logic (idt7133 only) r/ w lub ce l r/ w llb oe l i/o 0l - i/o 7l busy l a 0l ce l r/ w rub ce r r/ w rlb oe r i/o 8r -i/o 15r i/o 0r -i/o 7r busy r (1) a 0r ce r 2746 drw 01 a 10l address decoder a 10r i/o control address decoder 11 11 (1) i/o 8l -i/o 15l
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 2 2746 drw 02 10 11 12 13 14 15 16 idt7133/43 j68-1 / f68-1 (4) 68-pin plcc/flatpack top view (5) 50 49 48 47 46 45 44 index 17 18 19 20 21 22 23 24 25 26 51 52 53 54 55 56 57 58 59 60 987 6543 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a 6l a 5l a 4l a 3l a 2l a 1l a 0l a 0r a 1r a 2r a 3r a 4r a 5r busy l busy r ce l ce r i/o 9l i/o 10l i/o 11l i/o 13l i/o 14l i/o 15l v cc (1) i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r i/o 7r i / o 1 l i / o 2 l i / o 3 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 8 l v c c ( 1 ) a 1 0 l a 9 l a 8 l a 7 l r / w l l b o e l i / o 9 r i / o 1 0 r i / o 1 2 r i / o 1 3 r i / o 1 4 r i / o 1 5 r a 6 r a 7 r a 8 r a 9 r i / o 8 r a 1 0 r g n d ( 2 ) o e r r / w r l b r / w r u b i / o 1 1 r i / o 0 l i/o 12l gnd (2) r / w l u b pin configurations (1,2,3) ram or as a ?master? dual-port ram together with the idt7143 ?slave? dual-port in 32-bit-or-more word width systems. using the idt master/slave dual-port ram approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. both devices provide two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 1,150mw of power. low-power (la) versions offer battery backup data retention capability, with each port typically consuming 200w for a 2v battery. the idt7133/7143 devices have identical pinouts. each is packed in a 68-pin ceramic pga, 68-pin flatpack, 68-pin plcc and 100-pin tqfp. military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. notes: 1. both v cc pins must be connected to the power supply to ensure reliable operation. 2. both gnd pins must be connected to the ground supply to ensure reliable operation. 3. j68-package body is approximately 0.95 in x 0.95 in x 0.17 in. f68-package body is approximately 1.18 in x 1.18 in x 0.16 in. pn100-package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100999897969594939291908988878685848382818079787776 idt7133/43pf pn100-1 (4) 100-pin tqfp top view (5) n/c n/c n/c n/c i/o 10l i/o 11l i/o 12l i/o 13l gnd i/o 14l i/o 15l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r v cc i/o 4r i/o 5r i/o 6r n/c n/c n/c n/c 274 6 drw 03 n/c n/c n/c n/c a 5l a 4l a 3l a 2l a 1l a 0l n/c gnd n/c busy r n/c a 0r n/c n/c n/c n/c busy l a 1r a 2r a 3r a 4r i / o 9 l i / o 8 l i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l g n d i / o 1 l i / o 0 l o e l v c c r / w l l b c e l r / w l u b n / c n / c n / c a 1 0 l a 9 l a 8 l a 7 l a 6 l i / o 7 r i / o 8 r i / o 9 r i / o 1 0 r i / o 1 1 r i / o 1 2 r i / o 1 3 r i / o 1 4 r g n d i / o 1 5 r r / w r l b g n d n / c n / c a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r n / c n / c n / c o e r c e r r / w r u b ,
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 3 pin configurations (1,2,3) (con't.) notes: 1. both v cc pins must be connected to the power supply to ensure reliable operation. 2. both gnd pins must be connected to the ground supply to ensure reliable operation. 3. package body is approximately 1.18 in x 1.18 in x 0.16 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin names 2746 drw 04 i/o 0l v cc (1) a 10l a 9l a 8l a 7l a 6l a 5l a 4l a 3l 51 i/o 1l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l i/o 8l i/o 9l i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l i/o 15l v cc (1) gnd (2 ) i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r i/o 7r i/o 8r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r i/o 15r a 2l a 1l a 0l r/ w lub r/ w llb oe l a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r a 10r r/ w rlb r/ w rub oe r gnd (2) busy l busy r ce l ce r 50 48 46 44 42 40 38 36 a 0r a 1r 52 49 47 45 43 41 39 37 35 53 34 54 55 56 57 58 59 60 61 62 63 64 65 66 67 1 68 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 idt7133/43g gu68-1 (4) 68-pin pga top view (5) pin 1 designator abcde fgh jk l 01 02 03 04 05 06 07 08 09 10 11 left port right port names ce l ce r chip enable r/ w lub r/ w ru b upper byte read/write enable r/ w llb r/ w rlb lower byte read/write enable oe l oe r output enable a 0l - a 10l a 0r - a 10r address i/o 0l - i/o 15l i/o 0r - i/o 15r data input/output busy l busy r busy flag v cc power gnd ground 2746 tbl 01
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 4 capacitance (t a = +25c, f = 1.0mhz) recommended dc operating conditions maximum operating temperature and supply voltage (1,2) absolute maximum ratings (1) dc electrical characteristics over the operating temperature and supply voltage range (either port, v cc = 5.0v 10%) note: 1. at vcc < 2.0v, input leakages are undefined. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 10%. notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il (min.) = -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. symbol rating commercial & industrial military unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c p t (3 ) power dissipation 2.0 2.0 w i out dc output current 50 50 ma 2746 tbl 02 grade ambient temperature gnd vcc military -55 o c to +125 o c0v 5.0v + 10% commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 2746 tbl 04 symbol parameter (1 ) conditions (2 ) max. unit c in input capacitance v in = 3dv 11 pf c out output capacitance v out = 3dv 11 pf 2746 tbl 03 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1) ____ 0.8 v 2746 tbl 05 symbol parameter test conditions 7133sa 7143sa 7133la 7143la unit min. max. min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage (i/o 0 -i/o 15 )i ol = 4ma ___ 0.4 ___ 0.4 v v ol open drain output low voltage ( busy ) i ol = 16ma ___ 0.5 ___ 0.5 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2746 tbl 06
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 5 notes: 1. v cc = 5v, t a = +25c for typ., and are not production tested. i ccdc = 180ma (typ.) 2. 'x' in part number indicates power rating (sa or la) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/ t rc, and using ?ac test conditions" of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". dc electrical characteristics operating temperature and supply voltage range (2) (v cc = 5.0v 10%) 7133x20 7143x20 com'l only 7133x25 7143x25 com'l, ind & military 7133x35 7143x35 com'l, ind & military symbol parameter test condition version typ. (1) max. typ. (1) max. typ. (1) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled f = f max (3 ) com'l s l 250 230 310 280 250 230 300 270 240 210 295 250 ma mil & ind s l ____ ____ ____ ____ 250 230 330 300 240 220 325 295 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l s l 25 25 80 70 25 25 80 70 25 25 70 60 ma mil & ind s l ____ ____ ____ ____ 25 25 90 80 25 25 75 65 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (4 ) f=f max (3) active port outputs disabled com'l s l 140 120 200 180 140 100 200 170 120 100 180 160 ma mil & ind s l ____ ____ ____ ____ 140 100 230 190 120 100 200 180 i sb3 full standby current (both ports - cmos le ve l inputs) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4 ) com'l s l 1.0 0.2 15 5 1.0 0.2 15 4 1.0 0.2 15 4 ma mil & ind s l ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos le ve l inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5 ) v in > v cc - 0.2v o r v in < 0.2v active port outputs disabled f = f max (3 ) com'l s l 140 120 190 170 140 120 190 170 120 100 170 150 ma mil & ind s l ____ ____ ____ ____ 140 120 220 200 120 100 190 170 2746 tbl 07a 7133x45 7143x45 com'l & military 7133x55 7143x55 com'l, ind & military 7133x70/90 7143x70/90 com'l & military symbol parameter test condition version typ. (1 ) max. typ. (1 ) max. typ. (1 ) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled f = f max (3 ) com'l s l 230 210 290 250 230 210 285 250 230 210 280 250 ma mil & ind s l 230 210 320 290 230 210 315 285 230 210 310 280 i sb1 standb y curre nt (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l s l 25 25 75 65 25 25 70 60 25 25 70 60 ma mil & ind s l 25 25 80 70 25 25 80 70 25 25 75 65 i sb2 standb y curre nt (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (4) f=f max (3) active port outputs disabled com'l s l 120 100 190 170 120 100 180 160 120 100 180 160 ma mil & ind s l 120 100 210 190 120 100 210 190 120 100 200 180 i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) com'l s l 1.0 0.2 15 4 1.0 0.2 15 4 1.0 0.2 15 4 ma mil & ind s l 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5 ) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled f = f max (3 ) com'l s l 120 100 180 160 120 100 170 150 120 100 170 150 ma mil & ind s l 120 100 200 180 120 100 200 180 120 100 190 170 2746 tbl 07b
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 6 2746 drw 06 data out 775 ? 1250 ? 30pf 5v data out 775 ? 1250 ? 5pf* 5v busy 270 ? 30pf 5v data retention waveform ac test conditions data retention characteristics (la version only) v lc = 0.2v, v hc = v cc - 0.2v notes: 1. vcc = 2v, t a = +25c, and are not production tested. 2. t rc = read cycle time 3. this parameter is guaranteed by device characterization but is not production tested. figure 2. output load (for t lz , t hz , t wz , t ow ) *including scope and jig figure 1. ac output test load figure 3. busy output load (idt7133 only) 7133la/7143la symbol parameter test condition min. typ. (1) max. unit v dr v cc for data rete ntion v cc = 2v 2.0 ___ ___ v i ccdr data re te ntion current ce > v hc v in > v hc or < v lc mil. & ind. ___ 100 4000 a com'l. ___ 100 1500 t cdr (3 ) chip de select to data retentio n time 0 ___ ___ v t r (3 ) operation recovery time t rc (2) ___ ___ v 2746 tbl 08 input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns max. 1.5v 1.5v figures 1, 2 and 3 2746 tbl 09 2746 drw 05 t cdr t r ce v cc data retention mode v dr v dr > 2v 4.5v 4.5v v ih v ih
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 7 ac electrical characteristics over the operating temperature and supply voltage (3) notes: 1. transition is measured 0mv fromlow or high-impedance voltage with load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. 'x' in part number indicates power rating (sa or la). 7133x20 7143x20 com'l only 7133x25 7143x25 com'l, ind & military 7133x35 7143x35 com'l, ind & military unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 12 ____ 15 ____ 20 ns t oh output hold from address change 0 ____ 0 ____ 0 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 20 ns t pu chip enable to power up time (2 ) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2 ) ____ 20 ____ 50 ____ 50 ns 2746 tbl 10a 7133x45 7143x45 com'l & military 7133x55 7143x55 com'l, ind & military 7133x70/90 7143x70/90 com'l & military unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 45 ____ 55 ____ 70/90 ____ ns t aa address access time ____ 45 ____ 55 ____ 70/90 ns t ace chip enable access time ____ 45 ____ 55 ____ 70/90 ns t aoe output enable access time ____ 25 ____ 30 ____ 40/40 ns t oh output hold from address change 0 ____ 0 ____ 0/0 ____ ns t lz output low-z time (1,2) 0 ____ 5 ____ 5/5 ____ ns t hz output high-z time (1,2) ____ 20 ____ 20 ____ 25/25 ns t pu chip enable to power up time (2 ) 0 ____ 0 ____ 0/0 ____ ns t pd chip disable to power down time (2 ) ____ 50 ____ 50 ____ 50/50 ns 2746 tbl 10b
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 8 timing waveform of read cycle no. 1, either side (5) timing waveform of read cycle no. 2, either side (5) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is deasserted first, oe or ce . 3. t bdd delay is required only in a case where the opposite port is completing a write operation to the same address location. for sim ultaneous read operations, busy has no relationship to valid output data. 4. start of valid data depends on which timing becomes effective last, t aoe , t ace , t aa, or t bdd . 5. r/w = v ih , and the address is valid prior to or coincidental with ce transition low. 2746 drw 07 t aa t oh t oh data out address t rc data valid previous data valid busy out t bdd (3,4) 2746 drw 08 t aoe t lz t hz data out ce t ace valid data oe current i cc i sb t pu 50% t lz t pd 50% t hz (1) (4) (1) (4) (2) (2)
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 9 ac electrical characteristics over the operating temperature and supply voltage (5) notes: 1. transition is measured 0mv from low or high-impedance voltage from the output test load (figure 2). 2. this parameter is guaranteed by device characterization but not production tested. 3. for master/slave combination, t wc = t baa + t wr + t wp , since r/ w = v il must occur after t baa. 4. the specification for t dh must be met by the device supplying write data to the ram under all operation conditions. although t dh and t ow values will very over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part number indicates power rating (sa or la). symbol parameter 7133x20 7143x20 com'l only 7133x25 7143x25 com'l, ind & military 7133x35 7143x35 com'l, ind & military unit min. max. min. max. min. max. wri t e cycl e t wc write cycle time (3) 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ 25 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 25 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ 25 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ 20 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 20 ns t dh data ho ld time (4) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 12 ____ 15 ____ 20 ns t ow outp ut active fro m end-of-write (1 , 2,4) 0 ____ 0 ____ 0 ____ ns 2746 tbl 11a symbol parameter 7133x45 7143x45 com'l & military 7133x55 7143x55 com'l, ind & military 7133x70/90 7143x70/90 com'l & military unit min. max. min. max. min. max. wri t e cycl e t wc write cycle time (3) 45 ____ 55 ____ 70/90 ____ ns t ew chip enable to end-of-write 30 ____ 40 ____ 50/50 ____ ns t aw address valid to end-of-write 30 ____ 40 ____ 50/50 ____ ns t as address set-up time 0 ____ 0 ____ 0/0 ____ ns t wp write pulse width 30 ____ 40 ____ 50/50 ____ ns t wr write recovery time 0 ____ 0 ____ 0/0 ____ ns t dw data valid to end-of-write 20 ____ 25 ____ 30/30 ____ ns t hz output high-z time (1,2) ____ 20 ____ 20 ____ 25/25 ns t dh data ho ld time (4) 5 ____ 5 ____ 5/5 ____ ns t wz write enable to output in high-z (1,2) ____ 20 ____ 20 ____ 25/25 ns t ow outp ut active fro m end-of-write (1 , 2,4) 5 ____ 5 ____ 5/5 ____ ns 2746 tbl 11b
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 10 ac electrical characteristics over the operating temperature and supply voltage (6) notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read and busy". 2. t bdd is calculated parameter and is greater of 0, t wdd - t wp (actual) or t ddd - t dw (actual). 3. to ensure that the earlier of the two ports wins. 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 'x' in part number indicates power rating (sa or la). 7133x20 7143x20 com'l only 7133x25 7143x25 com'l, ind & military 7133x35 7143x35 com'l, ind & military symbol parameter min. max. min. max. min. max. unit busy timing (for master 71v33) t baa busy access time from address ____ 20 ____ 20 ____ 30 ns t bda busy disable time from address ____ 20 ____ 20 ____ 30 ns t bac busy access time from chip enable ____ 20 ____ 20 ____ 25 ns t bdc busy disable time from chip enable ____ 17 ____ 20 ____ 25 ns t wdd write pulse to data delay (1) ____ 40 ____ 50 ____ 60 ns t ddd write data valid to read data delay (1 ) ____ 30 ____ 35 ____ 45 ns t bdd busy disable to valid data (2 ) ____ 25 ____ 30 ____ 35 ns t aps arbitration priority set-up time (3 ) 5 ____ 5 ____ 5 ____ ns t wh write hold after busy (5) 20 ____ 20 ____ 25 ____ ns busy input timing (for slave 71v43) t wb busy input to write (4 ) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 20 ____ 20 ____ 25 ____ ns t wdd write pulse to data delay (1) ____ 40 ____ 50 ____ 60 ns t ddd write data valid to read data delay (1 ) ____ 30 ____ 35 ____ 45 ns 2746 tbl 12a 7133x45 7143x45 com'l & military 7133x55 7143x55 com'l, ind & military 7133x70/90 7143x70/90 com'l & military symbol parameter min.max.min.max.min.max.unit busy timing (for master 71v33) t baa busy access time from address ____ 40 ____ 40 ____ 45/45 ns t bda busy disable time from address ____ 40 ____ 40 ____ 45/45 ns t bac busy access time from chip enable ____ 30 ____ 35 ____ 35/35 ns t bdc busy disable time from chip enable ____ 25 ____ 30 ____ 30/30 ns t wdd write pulse to data delay (1) ____ 80 ____ 80 ____ 90/90 ns t ddd write data valid to read data delay (1 ) ____ 55 ____ 55 ____ 70/70 ns t bdd busy disable to valid data (2 ) ____ 40 ____ 40 ____ 40/40 ns t aps arbitration priority set-up time (3 ) 5 ____ 5 ____ 5/5 ____ ns t wh write hold after busy (5) 30 ____ 30 ____ 30/30 ____ ns busy input timing (for slave 71v43) t wb busy input to write (4 ) 0 ____ 0 ____ 0/0 ____ ns t wh write hold after busy (5) 30 ____ 30 ____ 30/30 ____ ns t wdd write pulse to data delay (1) ____ 80 ____ 80 ____ 90/90 ns t ddd write data valid to read data delay (1 ) ____ 55 ____ 55 ____ 70/70 ns 2746 tb l 1 2b
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 11 notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. timing depends on which enable signal is de-asserted first, ce or oe . 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. r/ w for either upper or lower byte. write cycle no. 2 ( ce controlled timing) (1,5) timing waveform of write cycle no. 1 (r/ w controlled timing) (1,5,8) ce 2746 drw 09 t aw t as t wr t dw data in address t wc r/ w t wp t dh data out t wz (7) (4) (2) t ow oe (9) t lz (7) t hz (6) (3) (4) (7) t hz ce 2746 drw 10 t aw t as t wr t dw data in address t wc r/ w t ew t dh (9) (6) (2)
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 12 2746 drw 11 t dw t aps addr "a" t wc match t wp r/ w "a" data in"a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (4) t wdd data out "b" timing waveform of write with port-to-port read and busy (1,2,3) timing waveform of write with busy (3) notes: 1. t wh must be met for both busy input (idt7143, slave) and output (idt7133, master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. all timing is the same for left and right ports. port " a " may be either left or right port. port " b " is the opposite from port " a ". notes: 1. to ensure that the earlier of the two ports wins, t aps is ignored for slave (idt7143). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 2746 drw 12 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (1) (2) ,
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 13 timing waveform of busy arbitration controlled by ce timing (1) timing waveform of busy arbitration controlled by addresses (1) notes: 1. all timing is the same for left and right ports. port " a " may be either the left or right port. port " b " is the port opposite from port " a ". 2. if t aps is not satisfied, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (idt7133 only). t aps (2) 2746 drw 13 addr "a" and "b" addresses match ce "b" busy "b" t bac t bdc ce "a" t rc 2746 drw 14 addr "a" addresses match addr "b" busy "b" addresses do not match t wc or t aps t baa t bda (2)
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 14 functional description the idt7133/43 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt7133/43 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. non-contention read/write conditions are illustrated in truth table 1. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by using the idt7143 (slave). in the idt7143, the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 7133 ram are open drain and require pull- up resistors. width expansion with busy logic master/slave arrays when expanding an idt7133/43 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt7133 ram the busy pin is an output and on the idt7143 ram, the busy pin is an input (see figure 3). expanding the data bus width to 32 bits or more in a dual-port ram system implies that several chips will be active at the same time. if each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its busy l while another activates its busy r signal. both sides are now busy and the cpus will await indefinitely for their port to become free. to avoid the ?busy lock-out? problem, idt has developed a master/slave approach where only one hardware arbitrator, in the master, is used. the slave has busy inputs which allow an interface to the master with no external components and with a speed advantage over other systems. when expanding dual-port rams in width, the writing of the slave rams must be delayed until after the busy input has settled. otherwise, the slave chip may begin a write cycle during a contention situation. conversely, the write pulse must extend a hold time past busy to ensure that a write cycle takes place after the contention is resolved. this timing is inherent in all dual-port memory systems where more than one chip is active at the same time. the write pulse to the slave should be delayed by the maximum arbitration time of the master. if, then, a contention occurs, the write to the slave will be inhibited due to busy from the master. figure 4 . busy and chip enable routing for both width and depth expansion with the idt7133 (master) and the idt7143 (slave). v cc r/ w busy r/ w busy idt7133 master v cc r/ w busy r/ w busy r/ w busy r/ w busy left right 2746 drw 15 idt7143 slave 270 ? 270 ?
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 15 truth table i ? non-contention read/write control (4) truth table ii ? address busy arbitration notes: 1. pins busy l and busy r are both outputs on the idt7133 (master). both are inputs on the idt7143 (slave). on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. ?h? if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = v il will result busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. notes: 1. a 0l - a 10l a 0r - a 10r 2. if busy = low, data is not written. 3. if busy = low, data may not be valid, see t wdd and t ddd timing. 4. "h" = high, "l" = low, "x" = don?t care, "z" = high-impedance, "lb" = lower byte, "ub" = upper byte left or right port (1 ) function r/ w lb r/ w ub ce oe i/o 0-7 i/o 8-15 x x h x z z port disabled and in power down mode, i sb2 , i sb4 xxhx z zce r = ce l = v ih , po we r down mo de, i sb1 or i sb3 lllxdata in data in data o n lower byte and up per byte writte n into memory (2 ) lhll data in data out data on lo we r byte written into memo ry (2) , data in memory output on upper byte (3 ) hlll data out data in data in memory output on lower byte (3) , data on uppe r byte written into memory (2 ) lhlhdata in z data on lower byte written into memory (2) hllh z data in data on upp er byte written into me mory (2 ) hhl ldata out data out data in memory output on lower byte and upper byte h h l h z z high impedance outputs 2746 tbl 13 inputs outputs function ce l ce r a 0l -a 10l a 0r -a 10r busy l (1 ) busy r (1 ) xxno matchhhnormal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3 ) 2746 tbl 14
6.42 idt7133sa/la, idt7143sa/la high-speed 2k x 16 dual-port ram military, industrial and commercial temperature ranges 16 ordering information xx power xx speed x package x process/ temperature range blank i (1) b commercial (0 cto+70 c) industrial (-40 cto+85 c) military (-55 c to +125 c) j g f pf 68-pin plcc (j68-1) 68-pin pga (gu68-1) 68-pin flatplack (f68-1) 100-pin tqfp (pn100-1) 20 25 35 45 55 70 90 xxxx device type idt speed in nanoseconds 2746 drw 16 la sa low power standard power 7133 7143 32k (2k x 16-bit) master dual-port ram 32k (2k x 16-bit) slave dual-port ram commercial only commercial, industrial & military commercial, industrial & military commercial & military commercial, industrial & military commercial & military commercial & military , x g green compliant to mil-prf-38535 qml (2) the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 12/18/98: initiated datasheet document history converted to new format cosmetic and typographical corrections added additional notes to pin configurations page 2 corrected pn100 pinout 02/17/99: corrected pf ordering code 030/9/99: cosmetic and typographical corrections 06/09/99: changed drawing format 10/01/99: added industrial temperature ranges and removed corresponding notes 11/10/99: replaced idt logo 04/01/00: changed 500mv to 0mv in notes page 2 fixed overbar in pinout 06/26/00: page 4 increased storage temperature parameters clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" 01/31/06: page 1 added green availability to features page 16 added green indicator for ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com notes: 1. contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office.

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